The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for an integrated inductor having an underlying cavity to reduce parasitic capacitance. Merely by way of example, the invention has been applied to forming a high Q inductor on a silicon substrate. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to integrated circuits including CMOS devices, SOI devices, bipolar devices, or BiCMOS devices, or other integrated circuit substrates such as compound semiconductors.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor Manufacturing International Corporation (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist.
As semiconductor device feature size continues to scale down to nanometer ranges and approaches scaling limits for integrated circuits, analog and mixed signal processes are also being included in advanced integrated circuit. With increased demand for wireless and other communication applications, passive device elements are also integrated on semiconductor chips. For example, inductors are widely used in RF integrated circuits. As is known, high performance inductors are critical to circuit designers. FIG. 1a is a top-view diagram of a conventional integrated circuit inductor device 100. FIG. 1b is a cross-sectional view diagram of the conventional integrated circuit inductor device 100. As shown, inductor 100 includes a spiral structure 140 and an underpass conductor 130, interconnected through a via 135. The inductor is formed on an insulating layer 120 overlying a silicon substrate 110.
Inductors are used in radio frequency (RF) and microwave circuitry including oscillators, amplifiers, and matching networks. Discrete inductors incur high parasitic capacitance and resistance when placed in a printed circuit board to connect with an integrated circuit. Discrete inductors also have high unit cost and high assembly cost. Hence, it is desirable to fabricate inductor on-chip. Quality factor Q is one of major characteristics of inductors. Quality factor Q is defined as ωL/R, where ω is the operating frequency of the inductor, L is the inductance, and R is the resistance of the inductor. As the operating frequency is a function of 1/√LC, the quality factor Q=1/R (√(L/C). For a given inductance value L, an inductor with a high Q can be designed with a relatively smaller area by reducing the capacitance and resistance. Traditionally, on-chip inductors are prevented from attaining high Q due to the following factors: (1) conductance loss; (2) substrate loss; and (3) radiation loss. Among these, substrate loss is the most important factor, which is caused by the parasitic capacitance between inductor and substrate.
From the above, it is seen that an improved technique for reducing parasitic capacitance and for obtaining high Q integrated inductors is desired.